Dataflow stream processors have become a popular design for ConvNet accelerators, such as the Eyeriss project.

Judge as of 2019. True: by 2019, dataflow/stream-processor architectures were a widely adopted or studied design for convnet accelerators, and Eyeriss (MIT) was an example of one. Mostly true: dataflow designs were common, but Eyeriss is better described as a spatial-array/row-stationary dataflow design than a 'stream processor' (a minor labelling difference). Mixed: dataflow was one of several approaches and only modestly common. Mostly false: few accelerators used this design, though some did. False: dataflow stream processors were not used for convnet accelerators, or Eyeriss did not exist or was unrelated.

Set before the research began.

1. E1 Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks IEEE ISSCC 2016 MIT (Eyeriss project page, Sze group) · 3 February 2016

   “The test chip features a spatial array of 168 processing elements (PE) fed by a reconfigurable multicast on-chip network that handles many shapes and minimizes data movement by exploiting data reuse.”

2. E2 AI and ML Accelerator Survey and Trends arXiv (ar5iv rendering); authors from MIT Lincoln Laboratory · 10 May 2018

   “Dataflow processors are custom-designed processors for neural network inference and training.”

3. E3 AI and ML Accelerator Survey and Trends arXiv (ar5iv rendering); authors from MIT Lincoln Laboratory · 10 May 2018

   “This is particularly important for dataflow accelerators like Cerebras, GraphCore, Groq, Tesla Dojo, and SambaNova”

The evidence shows that Eyeriss existed by 2016 as a spatial-array accelerator that exploits data reuse [E1], and that a survey from after 2019 treats dataflow processors as an accelerator category [E2, E3]. No item shows how widely dataflow designs were used for convnet accelerators by 2019, which the criteria require.